One prior-art power hybrid integrated circuit is known (U.S. Pat. No. 4,737,235), comprising dielectric board having a topological metallization pattern and a number of recesses, wherein semiconductor chips are fixed by means of a binder so that the surfaces of the chips having bonding pads are coplanar with the board surface, and the chip bonding pads are electrically connected to the topological metallization pattern.
The circuit construction mentioned above has a small area of chip-to-board heat transfer and hence an inadequate heat dissipating capacity.
One more prior-art hybrid integrated circuit is known (EP, A, 0334397), comprising a double-side metallized dielectric board with a topological metallization pattern on the face side and with at least one mounting pad located in a recess of the face board side on a heat sink which is essentially a system of holes in the recess bottom, the holes being filled with a heat conducting material. The board is joined with its back side to a heat conducting base, the naked electronic chip is placed on and fixed to the recess in the mounting pad so that the chip face surface is coplanar with the topological metallization pattern.
This circuit construction cannot make use of a broad range of semiconductor devices.